J. Zhang, W. Bian and H. Zhang, A Low-Latency, Highly-Pipelined Hardware Architecture for H.266/VVC Dependent Quantization
发布时间：2025-09-21
点击次数：
发表刊物：IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 72, no. 8, pp. 4040-4051, Aug. 2025, doi: 10.1109/TCSI.2025.3575567.
关键字：Quantization (signal);Transforms;Encoding;Hardware;Syntactics;Distortion;Mathematical models;Estimation;Costs;Computer architecture;H.266/VVC;dependent quantization;hardware pipeline;FPGA;rate estimate
论文类型：期刊论文
是否译文：否