A Simple Approach to Reject DC Offset for Single-Phase Synchronous Reference Frame PLL in Grid-Tied Converters
发布时间：2021-07-28
点击次数：
影响因子：3.367
DOI码：10.1109/ACCESS.2020.3003009
发表刊物：IEEE Access
关键字：Phase locked loops; Band-pass filters; Frequency estimation; Resonant frequency; Inverters; Periodic structures; Frequency synchronization; DC offset; inverters; phase-locked loop (PLL); second order generalized integral
摘要：Synchronous reference frame phase-locked loop (SRF-PLL) is widely used for grid voltage synchronization in single-phase grid-connected power converters. However, in the actual situation, dc offset component may be introduced in the input of the PLL, due to the transient fault of the power grid, sampling and measurement error, or A/D signal processing. A simple yet effective approach with additional all-pass filter based dc rejecter is presented for SRF-PLL, in this paper. Thereby, correct estimation and undesirable periodic ripple free can be achieved in SRF-PLL, when the input signal contains dc offset. The second order generalized integrator based PLL (SOGI-PLL) is first introduced, followed by the analysis on influence of the input dc offsets in SRF-PLL. The structure of enhanced-SOGI (ESOGI) with its analysis of dc offset rejection effects and performance have been then formulated in detail. Finally, experimental results are presented to demonstrate the effectiveness of the proposed ESOGI based PLL.
合写作者：An, Mengjun, Wang, Hui*, Zhang, Zhigang, Xu, Chenhua, Song, Shaojian, Lv, Zhilin
第一作者：Liu, Bin
论文类型：期刊论文
通讯作者：Chen, Yanming
论文编号：19799200
学科门类：工学
一级学科：电气工程
文献类型：J
卷号：8
页面范围：112297-112308
ISSN号：2169-3536
是否译文：否
发表时间：2020-01-01
收录刊物：SCI、EI
附件：